CIQA

In the n=5 block, q1 participates in more two-qudit gates than any other position: it is the junction between both parity checks, which means it accumulates gate noise from both. On current hardware (typical two-qudit gate error ~1%), this can prevent both parity ancilla from firing correctly in the same shot, causing q1 errors to go undetected. Qudits q0, q2, q3, and q4 each participate in one parity check and are not affected by this. This is a hardware fidelity constraint at current gate error rates, not a structural flaw in the encoding. Lower gate error rates or hardware topologies that natively support all required connections without SWAP insertion will resolve this.

Concatenation re-encodes every physical qudit of an encoded block into its own CIQA block. Each level multiplies the qubit count by n and reduces the logical error rate from p_L to p_L squared. To concatenate: run encode on your logical circuit to get the level-1 physical circuit, then pass that output as the input to another encode call with the same n and d. Repeat for each additional level. The coupling map at each level must accommodate the full expanded qubit count plus ancilla (n data + (n-1) ancilla per logical qubit at n=5).